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r19ds0068ej0200 rev.2.00 page 1 of 22 jul 06, 2012 preliminary datasheet hd49343np/hnp cds/pga & 12-bit a/d converter description the hd49343np/hnp is a cmos ic that provides cds-pg a analog processing (cds/p ga) suitable for ccd camera digital signal processing syst ems together with a 12-bit a/ d converter in a single chip. functions ? correlated double sampling ? pga ? serial interface control ? 12-bit adc ? operates using only the 3 v, adc output ? corresponds to switching mode of power dissipation and operating frequency hd49343hnp : 200 mw, f_max: 36 mhz hd49343np : 120 mw, f_max: 25 mhz ? qfn 36-pin package features ? suppresses the ccd reset noise by the correlated double sampling. ? high sensitivity can be achieved by 10 bit gray scal e provided by pga which can be set to ?6 to 34 db. ? pga gain, s/h frequency response, pulse timing, etc., is achieved via a serial interface. ? high precision is provided by a 12-bit resolution a/d converter. ? difference encoded gray code can be selected as an a/d output code. it is effective in suppression of solarization (wave pattern). it is patented by renesas. block diagram vrt a dc_in cds_in cds clamp adclk sp1 sp2 shc fbc d0 to d11 12 pblk obp vrb timing generator sck cs sdata serial comm dv dd av ss av dd dv ss pga 12bit adc differential code bias bias v_ref r19ds0068ej0200 rev.2.00 jul 06, 2012
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 2 of 22 jul 06, 2012 pin arrangement av ss 1 cds_in fbc shc bias av dd vrt vrb av ss 2 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 9 8 7 6 5 4 3 2 1 19 20 21 22 23 24 25 26 27 (top view) d11 d10 d9 d8 d7 d6 d5 d4 d3 sp2 adc_in sp1 obp pblk adclk dv ss 3 dv dd 3 dv dd 2 mon cs sdata sck dv dd 1 dv ss 12 d0 d1 d2 pin description pin no. symbol description i/o analog(a) or digital(d) remarks 1 to 9 34 to 36 d0 to d11 adc digital output (d0: lsb, d11: msb) o d 2 ma/10 pf 10 dv dd 2 digital power supply of adc output part (3 v) ? d 11 dv dd 3 digital power supply of timing generator part (3 v) ? d 12 dv ss 3 digital ground of timing generator part (0 v) ? d 13 adclk adclk input i d 14 pblk preblanking pulse input i d 15 obp obp input i d 16 sp1 sp1 input i d 17 adc_in adc input i d 18 sp2 sp2 input i d 19 av ss analog ground of cds, pga part (0 v) ? a 20 cds_in cds input pin (0.1 ? f) i a 21 fbc capacitor pin for feed back clamp (0.22 ? f for shc) o a 22 shc 47 ? + 1000 pf to ground ? a 23 bias bias current settings pin (33 k ? to ground) o a 24 av dd 2 analog power supply of adc part (3 v) ? a 25 vrt adc bias voltage of top side (0.1 ? f to ground) o a 26 vrb adc bias voltage of bottom side (0.1 ? f to ground) o a 27 av ss 2 analog ground of adc part (0 v) ? a 28 mon cp-sw, cpdm output o d 2 ma/10 pf 29 cs serial communication pulse cs input i d 30 sdata serial communication pulse sdata input i d 31 sck serial communication pulse sck input i d 32 dv dd 1 analog power supply of serial communication part (3 v) ? d 33 dv ss 12 ground of adc output part of serial communication part (0 v) ? d
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 3 of 22 jul 06, 2012 input/output equivalent circuit pin name equivalent circuit digital output d0 to d11, mon din dv dd stby digital output digital input pblk, obp, adclk, cs, sck, sdata digital input dv dd cds_in cdsin internally connected to vrt av dd analog vrt, vrb ? + ? + vrt2 vrt1 vrb av dd
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 4 of 22 jul 06, 2012 absolute maximum ratings (ta = 25 ? c) item symbol ratings unit power supply voltage v dd (max) 4.1 v power dissipation pt(max) 400 mw operating voltage v opr 2.7 to 3.45 v analog input voltage v in (max) ?0.3 to av dd +0.3 v digital input voltage v i (max) ?0.3 to dv dd +0.3 v operating temperature topr ?20 to +85 c storage temperature tstg ?55 to +125 c note: av dd 1, 2, av ss 1, 2 are analog power source series of cds, pga, adc. dv dd 1, dv ss 1 are digital power source series of serial communication. dv dd 2, dv ss 2 are digital power source series of adc output timing. dv dd 3, dv ss 3 are digital power source series of timing generator. electrical characteristics (unless otherwise specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v) ? cds_in, adc_in mode common items item symbol min typ max unit test conditions remarks v dd 2.70 3.00 3.45 v select vrt = 2.0 v power supply voltage range v dd2 3.10 3.30 3.45 v select vrt = 2.4 v f clk _hi 25 ? 36 mhz hd49343hnp conversion frequency f clk _low 5.5 ? 25 mhz hd49343np v ih2 dv dd 3.0 2.2 ? dv dd v digital input voltage v il2 0 ? dv dd 3.0 0.6 v all of digital input pins v oh dv dd ?0.5 ? ? v i oh = ?1 ma digital output pins digital output voltage v ol ? ? 0.5 v i ol = +1 ma i ih ? ? 50 ? a v ih = v dd digital input current i il ?50 ? ? ? a v il = 0 v adc resolution res ? 12 ? bit adc integral linearity inl ? (8) ? lsb f clk = 20 mhz adc differential linearity dnl ? (0.6) ? lsb f clk = 20 mhz *1 sleep current i slp ?100 ? 100 ? a digital input pin is set to 0 v, output pin is open standby current i stby ? 3 5 ma digital i/o pin is set to 0 v notes: 1. differential linearity is the calculated difference in linearity errors between adjacent codes. 2. values within parentheses ( ) are for reference.
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 5 of 22 jul 06, 2012 electrical characteristics (cont.) (unless otherwise specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v) ? items for cds_in mode item symbol min typ max unit test conditions remarks i dd1 ? (40) ? ma f clk = 36 mhz hd49343hnp consumption current i dd2 ? (25) ? ma f clk = 25 mhz hd49343np ccd offset tolerance range v ccd (?150) ? (150) mv t cds1 ? (1.5) ? ns t cds2 typ ? 0.8 1/4f clk typ ? 1.2 ns t cds3 ? (1.5) ? ns t cds4 typ ? 0.8 1/4f clk typ ? 1.2 ns t cds5 typ ? 0.85 1/2f clk typ ? 1.0 ns t cds6 ? (5) ? ns t cds7 11 ? ? ns t cds8 11 ? ? ns t cds9 ? (7) ? ns sampling timing specifications t cds10 ? (16) ? ns refer to table 4 clp(00) ? (56) ? lsb clp(09) ? (128) ? lsb clamp level clp(31) ? (304) ? lsb clamp level = settings value ? 8 + 56 pga(0) ?8 ?6 ?4 db pga(256) 2 4 6 db pga(512) 12 14 16 db pga(768) 22 24 26 db pga gain at cds_in pga(1023) 32 34 36 db at 1.0 v input, when pga output is 1v, it is defined as 0db note: values within parenthe ses ( ) are for reference. ? items for adc_in mode item symbol min typ max unit test conditions remarks i dd3 ? (30) ? ma f clk = 36 mhz consumption current i dd4 ? (20) ? ma f clk = 25 mhz t adc1 ? (6) ? ns t adc2 typ ? 0.85 1/2f adclk typ ? 1.15 ns t adc3 typ ? 0.85 1/2f adclk typ ? 1.15 ns t adc4 ? (14.5) ? ns timing specifications t adc5 ? (23.5) ? ns input current at adc input iin cin ?110 ? 110 ? a v in = 1.0 v to 2.0 v clamp level at adc input of2 1848 2048 2248 lsb gsl(0) ?8 ?6 ?4 db gsl(128) ?3 ?1 1 db gsl(256) 2 4 6 db gsl(384) 7 9 11 db pga gain at adc_in gsl(511) 12 14 16 db at 1.0 v input, when pga output is 1v, it is defined as 0db note: values within parenthe ses ( ) are for reference.
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 6 of 22 jul 06, 2012 internal functions functional description ? cds input ? ccd low-frequency noise is suppressed by cds (correlated double sampling). ? the signal level is clamped at 56 lsb to 304 lsb by resister during the ob period. * 1 ? gain can be adjusted using 10 bits of register within the range from ?6 to 34 db. ? automatic offset calibration of pga and adc ? dc offset compensation fe edback for ccd and cds ? pre-blanking ? digital output is fixed at clamp level. note: 1. it is not covered by warranty when 56 lsb settings. operating description figure 1 shows function block of this lsi. (gain setting) sh amp pga amp adc_in adc_in cds_in vrt sp1 sp1 sp2 c3 12bit adc b.g. ref ob clamp dm clamp offset calibration differential code vrt (2.0, 2.4v) vrb (1.0v) bias c2 c1 obp pblk shc fbc current dac lpf cds amp 12bit output cp-sw sp2 sp1 adclk figure 1 functional block diagram of cds/pga part 1. cds (correlated double sampling) circuit the cds circuit extracts the voltage differential between th e black level and a signal level. the black level is directly sampled at c1 by using the sp2 pulse, bu ffered by the shamp, then provided to the cdsamp. the difference between these two signal levels is extracted by the cdsamp, which also operates as a programmable gain amplifier at the previous stage. the cds input is biased with vrt (2.0 v or 2.4 v) during the pblk period, the above sampling and bias operation are paused. 2. pga circuit the pgamp is the programmable gain amplifier for the latter stage. the pgamp and the cdsamp set the gain using 10 bits of register. the equation below shows how the gain changes when register value n is from 0 to 1023. gain = ?6 db + 0.04 db ? n (log linear) 3. ob clamp feedback is done to set the black signal level input during the ob period to the dc standard, and all offsets (including the ccd offset and the cd samp offset) are compensated for. the offset from the adc output is calculated during the ob period, and shamp feedback capacitor c3 is charged by the current dac.
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 7 of 22 jul 06, 2012 serial interface specifications serial interface specifications sdata address data sck cs f sck d1d0 d3d2 d5d4 d7 d6 d9d8 d11d10 d13 d12 d15 d14 t int1 t int2 t su t ho latches sdata at sck rising edge data is determined at cs rising edge f sck t int1,2 t su t ho notes: 1. 2. 3. communication is 2 byte continuation communications. input 16 clocks of sck while cs is low. data is invalid if data transmission is aborted during transmission. min ? 50 ns 50 ns 50 ns max 5 mhz ? ? ? figure 2 serial interface timing specifications table 1 serial data function list d0 d1 d2 d3 d4 address 0 1 2 3 default value pga gain pga gain bias_sel d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 0000d4 0 d5 0 d6 0 d7 0 d8 0 d9 0 d10 0 d11 0 d12 0 d13 0 d14 0 d15 0 default value dummy clamp others dummy clamp others cpdm_th adc _in vrt sel vref off dll off cpdm_i 1100d4 0 d5 0 d6 0 d7 0 d8 0 d10 0 d11 0 d12 0 d13 d14 d15 0 default value filter lpf_sel shsw_sel sha_fsel slp 1000d4 1 d5 1 d6 0 d8 0 d9 0 d10 0 d11 1 d12 0 d13 1 d14 0 d15 0 stby remarks pga gain: ?6 to 34db (0.04db/step) d4: lsb, d13: msb d15, d14: bias_sel: when 0: biasing regularly, when 1cpdm: biasing after 2,3obp: 8clk biasing lpf_sel: lpf selection of 5 to 56mhz shsw_fsel, sha_fsel; sampling filter of sp1 part slp, stby: normally 0 settings cpdm_th/i: dummy clamp settings vrt_sel: 2.0/2.4v switching vref_off: bias off of vrt, vrb adc_in: adc input mode at 1 gray standard phase: move between 0 to 3clk adclk phase: positive/negative edge selection 10/12: bit number of gray conversion gry, difference: on/off of differential coded gray code gry_ref: 0 = 2 pixel standard, 1 = 1 pixel standard output fixation: test0, minv, linv (refer to hd49330 for details) clamp: setting value 8+56 obp_w: 8clk detection at 0, 4clk detection at 1 polar selection; 0 = negative, 1 = positive lo-pwr: guarantee 36mhz at 0, guarantee 25mhz at 1 calb: 1 offset calibration execution reset: software reset at 0, normally 1 settings default value clamp polar selection reset obp _w calb clamp re set lo- pwr 0100d4 1 d5 0 d6 0 d7 1 d8 0 d9 0 d10 0 d11 0 d12 0 obp inv polar selection pblk inv d13 1 d14 0 d15 1 4 default value differential code differential code output fixation standard phase adclk phase gry ref 10/ 12 test 0 minv gry differ ence 0010d4 0 d5 0 d6 0 d7 0 d7 0 d8 0 d9 0 d10 0 d11 0 d12 0 d13 0 linv 5 default value mon 1010d4 1 d5 1 d6 0 d8 0 d9 0 d10 0 d11 1 d12 0 d13 1 d14 0 d15 0 mon: cp-sw at 0, cpdm at 1
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 8 of 22 jul 06, 2012 table 1 serial data function list (cont.) note: address 15 is not in use. d0 d1 d2 d3 d4 address 6 default value new func cpad sel winck sel wide obp pblk act wob_ vth1 wob_ i clp_ i clp_hsel d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 0110d4d5 0 d6 0 d7 0 d7 0 d8 d9 0 d10 0 d11 0 d12 0 d13 0 d14 0 d15 0 7 default value test1 cpdm_dl cpdm_dl 1110d4 0 d5 0 d6 0 d8 0 d9 0 d10 0 d11 0 d12 0 d13 0 d14 0 d15 0 d7 8 default value 0001d4d5d6 d8d9d10d11d12d13d14 d15 d7 9 default value 1001d4d5d6 d8d9d10d11d12d13d14 d15 d7 0 11 default value 1101d4 0 d5 0 d6 0 d8 0 d9 0 d10 0 d11 0 d13 d14 test2 d7 0 12 default value 0011d4 0 d5 0 d6 0 d8 0 d9 0 d10 0 d11 0 d12 0 d13 0 d14 0 d15 0 test3 d7 0 13 default value 1011d4 0 d5 0 d6 0 d8 0 d9 0 d10 0 d11 0 d12 0 d13 0 d14 0 d15 0 test4 d7 0 14 default value 1 0 200a 20a 2a 1 400a 40a 4a 110d4 0 d5 0 d6 0 d8 0 d9 0 d10 0 d11 0 d12 0 d13 0 d14 0 d15 0 d7 10 default value 0101d4d5d6 d8d9d10 0 d11 0 d12 0 d13 0 d14 0 d15 0 wob_ vth1 wob_ vth2 wob_ vth3 remarks cpad sel: pad test. normally 0 settings winck sel: high clamp compensation window width 0: 32, 1: 64, 2: 128, 3: 16 wide_obp: correspond to wide ob pblk act: obp in a pblk period is valid wob_vth1: switching 200 a current of for wide ob 0: 63cnt, 1: 200cnt clp_hsel: continuing h number after high speed lead-in 0: 1h, 1: 2h, 2: 4h, 3: 8h wob_i: twice as current for wide ob clp_i: d15 = 1 1/2 half of normal clamp current iclp_th1 iclp_th2 iclp_th3 ? control of wide ob current value wob_i 0 15 127 511 1 63 255 1023 the number of counts wob_th1, 2, 3 2 200 511 infinity 3 infinity infinity infinity remarks only when an address 11 is 0, the setting value of an address 6 reflects the number of counts. test bit is bit for testing at the time of shipment in our company. usually, please set up an all 0 or do not transmit. d10: 1 pulse output regardless of the cpdm function. wob_vth1: switching 200 a current of for wide ob wob_vth2: switching 20 a current of for wide ob wob_vth3: switching 2 a current of for wide ob cpdm_dl: select 0 to 1016clk (every 4clk) (default value = 0, pulse stopping at all 1) pulse phase = data 4 (clk)
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 9 of 22 jul 06, 2012 explanation of serial data ? pga gain (d4 to d13 of address 0) refer to the p.4 block diagram for details. a gain shifts 3 db by voltage setup (d12 of address 4) of vrt. pga gain: ?6db + 0.04 db ? n (log linear) (1) at vrt = 2.0 v settings (cds input range is 1.4 vp-p) cds (cds is ?6 db) pga 0.04 db n adc 1 v 1.4 v 4095 (2) at vrt = 2.4 v settings (cds input range is 2.0 vp-p) cds (cds is ?6 db) pga 0.04 db n adc 1.4 v 2.0 v 4095 figure 3 level dia of pga 0 128 256 384 512 640 768 896 1023 (pga gain code) 40 gain (db) 30 34db 20 10 0 ?10 ?6db 31db ?9db (at vrt = 2.4v) (at vrt = 2.0v) figure 4 pga gain characteristics ? lpf_sel (d4 to d6 of address 1) frequency band restrictions of a cds input part are chosen. lpf_sel sensor frequency 0 6 mhz 1 12 mhz 2 18 mhz 3 25 mhz 4 30 mhz 5 35 mhz 6 40 mhz 7 50 mhz although s/n will rise if a frequency band is lowered, but opposite side amplifier operation becomes slow and which problem with line crawl and insufficient gain occurs. please choose a high point from the actually used frequency. about lfp_sel, followings are only testing guaranteed. (1) at low power mode: data = 3 (2) at normal power mode: data = 6
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 10 of 22 jul 06, 2012 ? shsw_fsel, sha_fsel (d8 to d13 of address 1) filtering processing is performed to the precharge part samp led by sp1. the cutoff frequency at this time can be chosen. table 1 shsw time constant setting table 2 shamp frequency characteristics setting shsw_fsel data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cutoff frequency (mhz) 72 69 63 60 54 51 45 42 36 33 27 24 18 15 9 6 sha_fsel data 0 1 2 3 cutoff frequency (mhz) 116 75 56 32 noise level shsw_fsel sha_fsel figure 5 the effect by shsw_fsel, sha_fsel note: s/n changes with data selections of shsw_fsel, sha_fs el, as shown in figure 5. please find the optimal value with evaluating a picture. ? slp and stby (d14, d15 of address 1) slp: stop the all of circuit. consumption current should below 10 ? a at cds section. when returning is necessary, please start up from an offset calibration {(3) of figure 6}. stby: operates with only a standard voltage generating circuit. consumption current is about 3 ma please expect about 20 h as time to stabilize a feedback clamp by return. ? clamp level (d4 to d8 of address 2) clamp level = setting data ? 8 + 56 d4: lsb, d8: msb default value is set to 9 ? 8 + 56 = 128
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 11 of 22 jul 06, 2012 ? clamp high-speed lead-in (d6, d7, d12, d13 of address 6) if a pga gain is changed, it will shift to high-speed lead -in operation automatically, and a feedback loop gain will be controlled by the magnification which set by d6 and d7. during end of the high speed lead-in to returning normal loop gain, high-speed lead-in m ode is continuing until h count number which set by d12, d13. (high-speed lead-in operation is continuing during offset error is more than 32 lsb, and it returns to normal loop gain in the h counter number which set by d12, d13 is countered.) in the usual clamp operation, the open loop differentiation gain ( ? gain/ ? h) of per 1 h is given by the lower formula. (1 h is 1 cycle of obp) ? gain/ ? h = 0.01/(fclk ? c3) (fclk: adclk frequency, c3: external capacity of fbc) ex): fclk = 20 mhz, c3 = 0.1 ? f ? ? gain/ ? h = 0.005 dc offset compensation amount per 1 h (lsb) = 0.005 ? offset error amount (lsb) * note: there is a maximum value in the above-mentioned amount of offset errors. on the other hand, in high-speed lead-i n operation, speed changes as follows. ex): fclk = 20 mhz, c3 = 0.1 ? f ? 32 ? ? gain/ ? h = 0.16 dc offset compensation amount per 1 h (lsb) = 0.16 ? offset error amount (lsb) when the error of about 500 lsb arises by high-speed lead-in operation, it can lead in a target clamp level by about 20 h. ? wide_obp (d9 of address 6) when d9 = 1, it corresponds to wide obp. when the width of obp is 63 1 or more clks, it recognizes automatically that it is wide and detection & compensation is performed every clk. in using this function, please contact to our company sales. ? obp_w (d9 of address 2) clamp detection is changed to 4 pixels at the time of 8 pixels and d9 = 1 at the time of d9 = 0. ? each polar selection (d10 to d12 of address 2) data name contents d11 obp_inv polar selection of obp. input the negative pulse at 0. i nput the positive pulse at 1. d12 pblk_inv polar selection of pblk input the negative pulse at 0. input the positive pulse at 1. pblk_inv is conjunction with sp_inv. ? low_pwr (d13 of address 2) it guarantees to sensor clk = 36 mhz at the time of d13 = 0. (hd49343hnp) it guarantees to sensor clk = 25 mhz at the time of d13 = 1. (hd49343np)
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 12 of 22 jul 06, 2012 ? calibration and reset (d14, d15 of address 2) by performing software reset and a calibration only once at the time of a power supply, a bias gap of an internal circuit is canceled automatically. (offset calibratio n) please be sure to perform by this lsi. an automatic offset calibration adjusts dc voltage of dac added to the output of pga amplifier. the clamp data (56 lsb to 304 lsb) based on a register setup is added to the data which cancels output offset of pga amplifier and input offset of adc, and it is given to this dac. automatic offset calibration starts automatically after the reset mode release by register setup, and it ends after 40000 (adclk). (in case of fclk = 20 mhz: 2.0 ms, in case of fclk = 10 mhz: 4.0 ms) v dd obp should the right phase obp is started in this period be stable in power supply voltage within the limits of operation. the input pulse should be normal. (1) reset = 0, calb = 0 (2) reset = 1, calb = 0 (3) all data transfer (4) calb = 1 (5) transfer the changed data since it is necessary to decide sp1, sp2, and an adclk phase before transmitting calb bit = 1, please perform this work with input pulse is stabilized. when offset calibration is needed, please avoid the v.blk period. ? ? : reset bit = transfer 0 it stands by 2 ms or more as charge time of an external capacitor. : reset bit = transfer 1 all registers are initialized. : transfer the resister which needs data changes. : automatic offset calibration is start. standby time is 40,000 or more adclks. : data, such as a pga gain, to change is transmitted. an address 2 is necessary to send after a calibration finishes, please set as reset = 1 and calb = 1. 1 ms or more a high-speed pulse should the right phase do not input obp before reset 2 ms or more (charge of external c) (1) 40,000 adclk (offset calibration) the contents of the above-mentioned serial data transmission are shown below. refer to the serial data specification table for the details of a register setup. 40,000adclk periods are spent for adjustment. it clears automatically after 40,000adclk(s) serial data transfer (2) (3) (4) (5) obp_in reset_bit (h/l is unfixed at the time of a power supply on) sp1,2_in adclk_in calb_bit figure 6 operation sequence of at power on
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 13 of 22 jul 06, 2012 ? dummy clamp (d4 to d8 of address 3) when a intense highlight like a solar is photoed, light leaks also to the ob part of a sensor and a clamp mistake is occurred. in order to prevent this incorrect operation, wh en the level difference of the ob part and a dummy part is supervised and it becomes the conditions of ob part > dummy part + cpdm_th, it changes to the clamp in a dummy level automatically. it becomes the amount of current whic h also set up simultaneously the feedback current at the time of dummy on by cpdm_i. the cpdm pulse for performing a dummy clamp is generated by the following formulas from delay of pblk. cpdm phase = pblk phase + (address 11) if a cpdm phase is set as the portion of shutter noise, it may incorrect-operate. when incorrect operation cannot be prevented, please turn off a function as cpdm_th = 0. moreover, since clamp mistake voltage is also changed by the pga gain, please control cpdm_th for a gain to be interlocked with. adc differential code digital output obp cp-sw sh amp cds pga cds_in vrt sp1 sp1 sp2 cpdm_i cpdm_th (clamp data) ? + ? + current cell pblk ob_det dm_det cpdm_dl cpdm_gen cpdm_i 0 1 2 3 contents 1/4 of current at normal time 1/8 of current at normal time 1/16 of current at normal time 1/32 of current at normal time cpdm_th 0 1 2 3 4 5 6 7 contents function off +128 +256 +384 +512 +640 +768 +896 figure 7 composition of dummy clamp circuit
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 14 of 22 jul 06, 2012 ? vrt_sel (d10 of address 3) when d10 = 0, vrt is 2.0 v, when d10 = 1, vrt is 2.4 v are chosen. however, when set to as d10 = 1, more than in 3.1 v av dd voltage as conditions. vrt_sel vrt voltage cds input range adc dynamic range av dd condition 0 2.0 v 1.4 vp-p 1.0 vp-p min = 2.7 v 1 2.4 v 2.0 vp-p 1.4 vp-p min = 3.1 v ? vref_off (d11 of address 3) at the time of d11 = 1, vrb and vrt intercept the supply fr om the inside of lsi, and the voltage supply from the outside becomes available. when making parallel connection, gain variation etc. can be suppressed by setting up as a master/a slave, as shown in the following figure. when external supply mode is chosen, please perform an offset calibration in the state of the voltage. 33k 33k bias bias 343 (master) 343 (slave) vrb vrt vrb vrt ? adc_in (d15 of address 3) when d15 = 0, normal cds operation mode, or when d15 = 1, adc_in mode for testing (b ias is about 1.0 v at this time) are chosen. ? mon (d4 of address 5) data mon pin 0 cp-sw 1 cpdm
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 15 of 22 jul 06, 2012 ? gray code (d4 to d10 of address 4) adc output code can be changed by differential coded gray sw (d7, d8) as followings. d7: 0 binary code :1 gray code d8: 0 normal :1 differential code when switching the several of adc out put at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. differential c ode and gray code are recommended for th is countermeasure. figure 8 indicates circuit block. when luminance signal changes are smoothly, the number of bit of switching digital output bit can be reduced and easily to reduce the ripple using this function. this function is especially effective for longer the settings of sensor more than clk = 30 mhz, and adc output. in using this code, a complex circuit is needed by the dsp side. figure 10 indicates the example. standard phase (d4) standard phase (d5) standard data output timing at differential code selected 0 0 third and fourth (third) 1 0 fourth and fifth (fourth) 0 1 fifth and sixth (fifth) 1 1 sixth and seventh (sixth) note: color filter is different from odd/even pixel, so considers 2 pixels of a head as a standard. when the inside of ( ) makes a standard 1 pixel. ? adclk phase (d6): ad clk polarity to obp when 0: select positive edge when 1: select negative edge ? 10/12 (d9): binary ? gray convert bit number when 0: select 12 bit when 1: select 10 bit ? gry_ref (d10): the number of standard pixel when 0: select 2 pixel when 1: select 1 pixel adc 12 12 differential sw (d8) carry bit rounding + ? gray sw (d7) standard data control signal (d4,d5,d6) standard data selector output 2clk_dl 1clk_dl binarygray conversion (10/12 bit) 10/12 bit conversion (d9) the number of standard pixel (d10) figure 8 differential code, gray code circuit 21 a dclk obp digital output (falling edge of obp and standard edge of adclk should be exept 5 ns) (in case of select the positive edge of adclk by d6) differential data standard data differential data (in case of select the negative polar) 34567 8 figure 9 timing specification of differential code (1) complex differential coded from adc standard data control signal carry bit rounding standard data selector d11 d11 d10 d9 d0 d10 d9 d0 2clk delay (2) convert gray binary convert gray binary figure 10 complex circuit example at the dsp side
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 16 of 22 jul 06, 2012 ? horizontal timing notes: 1. 2. 3. 4. duty of clk_in should be less than 50 15%. the rising edge of sp1 and the edge of pblk should not overlap. (should not be within 5ns.) each pulse is indicated on the basis of negative polarity. cpdm cannot be made from a set without pblk. differential code standard a dc output clamp level signal output sp1 ob detection (8/4clk) cpdm_dl 4(clk) when it observes with a mon terminal, cpdm is late 4clks. pblk obp 5clk 2clk+setting value 2clk 11clk 4clk detection cpdm signal output figure 11 the timing of h.blk period ? vertical timing cpdm obp pblk figure 12 the timing of v.blk period
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 17 of 22 jul 06, 2012 pipeline delay the output timing figure at the time of using each input terminal of cds_in and adc_in for figure 13 is shown. d0 to d11 d0 to d11 012 91 0 11 n+1 n+2 n+9 n+10 n+11 n cds_in sp1 sp2 adclk n+2 n+8 n+9 n+10 n+11 n?8 n?9n ?1 adc_in adclk n n+1 n n+1 n?9n ?8n ?1 n n?10 ? cds_in input mode in use ? adc_in input mode in use ~ figure 13 output timing figure at the time of us ing each input terminal of cds_in and adc_in ? as for an adc output (d0 to d11), both input mode is outputted by the rising edge of adclk. ? the pipeline delay at the time of cdsin in use is 10 clocks and adc_in in use is 9 clocks. ? the input signal sampling at the time of adc_in input mode is performed by the rising edge of adclk. ? the pipeline delay increases 1 more clock when using the differential code.
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 18 of 22 jul 06, 2012 detailed timing specifications detailed timing specifications when cds_in mode is used figure 14 shows the detailed timing specifications when the cds_in input mode is used, and table 4 shows each timing specification. black level signal level d0 to d11 cds_in sp1 vth (2) (3) sp2 a dclk (7) vth vth (8) (9) (10) (4) (1) (5) (6) figure 14 detailed timing chart when cds_in input mode is used table 4 timing specifications when the cds_in input mode is used no. timing symbol min typ max unit (1) black-level signal fetch time t cds1 ? (1.5) ? ns (2) sp1 low period t cds2 typ ? 0.8 1/4f clk typ ? 1.2 ns (3) signal-level fetch time t cds3 ? (1.5) ? ns (4) sp2 low period t cds4 typ ? 0.8 1/4f clk typ ? 1.2 ns (5) sp1 rising to sp2 rising time t cds5 typ ? 0.85 1/2f clk typ ? 1.00 ns (6) sp1 rising to adclk rising inhibition time t cds6 ? (5) ? ns (7), (8) adclk t wh min./t wl min. t cds7, 8 11 ? ? ns (9) adclk rising to digital output hold time t chld9 ? (7) ? ns (10) adclk rising to digital output delay time t cod10 ? (16) ? ns notes: 1. the value specified on freque ncy of operation is the case where "t cds5 " is being protected. even if the frequency used is in specification, when this time is short, it becomes equivalent to the operation of high frequency. moreover, please set up max of t cds5 as 1/2f clk . 2. sp1 at the time of single sampling mode ne eds to set it as the phase shifted 180 to sp2. obp detailed timing specifications figure 15 shows the obp detailed timing specifications. the ob period is from the fifth to the twelfth clock cycle after the ob pulse is input. the average of the black signal level is taken for eight input cycles during the ob period and becomes the clamp level (dc standard). cds_in obp note: ob pulse > 2 clock ob period * 1 1. shifts 1 clock cycle depending on the obp input timing. n n+1 n+5 n+12 n+13 figure 15 obp detailed timing specifications
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 19 of 22 jul 06, 2012 detailed timing specifications at pre-blanking figure 16 shows the pre-blanking detailed timing specifications. digital output (d0 to d11) adc data clamp level adc data pblk adclk 2 clocks adclk 11 clocks vth v ol v oh figure 16 detailed timing specifications at pre-blanking detailed timing specifications when adc_in input mode is used figure 17 shows the detailed timing chart when adc_in input mode is used, an d table 5 shows each timing specification. a dc_in (1) a dclk d0 to d11 (2) vth v dd /2 (3) (5) (4) figure 17 detailed timing chart when adc_in input mode is used table 5 timing specifications when adc_in input mode is used no. timing symbol min typ max unit (1) signal fetch time t adc1 ? (6) ? ns (2), (3) adclk t wh min./t wl min. t adc2, 3 typ ? 0.85 1/2f adclk typ ? 1.15 ns (4) adclk rising to digital output hold time t ahld4 ? (14.5) ? ns (5) adclk rising to digital output delay time t aod5 ? (23.5) ? ns
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 20 of 22 jul 06, 2012 example of external circuit ? cds_in mode 17 19 20 21 22 23 24 25 26 27 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 18 29 34 35 36 33 32 31 30 28 from tg to dsp from ccd 3.0 v or 3.3 v from micro computer 47 33 k 0.1 0.1 33/6 hd49343np/hnp (cds/pga+adc) ? adc_in mode av ss1 cds_in fbc shc bias av dd vrt vrb av ss2 d11 d10 d9 d8 d7 d6 d5 d4 d3 sp2 adc_in sp1 obp pblk adclk dv ss3 dv dd3 dv dd2 mon cs sdata sck dv dd1 dv ss12 d0 d1 d2 47 47 1000 p 0.1 0.1 0.1 0.1 + 33/6 + 17 19 20 21 22 23 24 25 26 27 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 18 29 34 35 36 33 32 31 30 28 from tg from input signal to dsp 3.0 v or 3.3 v from micro computer 47 33 k 0.1 0.1 33/6 hd49343np/hnp (cds/pga+adc) av ss1 cds_in fbc shc bias av dd vrt vrb av ss2 d11 d10 d9 d8 d7 d6 d5 d4 d3 sp2 adc_in sp1 obp pblk adclk dv ss3 dv dd3 dv dd2 mon cs sdata sck dv dd1 dv ss12 d0 d1 d2 47 47 1000 p 0.1 0.1 0.1 0.1 + 33/6 +
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 21 of 22 jul 06, 2012 check item please check following items for use. no. item contents judgment 1 input pulse polarity are the polarity of obp and pblk and the polarity set as d11-d12 of an address 2 match? do sp1 and sp2 keep the relation of figure 14 and table 4? note: since especially tcds5 becomes equivalent to frequency of operation. moreover, as for sp1 and sp2, a low period should not overlap. is the adclk rising set up near sp1 falling edge? (figure 14, table 4) are an adclk rising and obp falling edge separated ? 5 ns or more? (figure 9) 2 input pulse timing is the margin for ? 5 ns or more in the edge of the adclk rising to pblk? is it satisfactory to an obp phase and a cpdm phase? (figure 11 and 12) is a margin in the latch phase of an adc output and dsp? 3 output timing when using differential code, does not a standard signal phase have a problem? (figure 9 and 11) 4 power supply voltage when vrt voltage = 2.4 v are chos en, more than vdd = 3.1 v is required. 5 offset calibration is the offset calibration of figure 6 performed at the time of a power on? adjustment of sp1 and sp2 phase. adjustment of an adclk phase. when adjustment finishes, re-check about item 2. 6 s/n improvement filter adjustment of lpf_sel, shsw_fsel, and sha_fsel. the capacitor of fbc becomes the relation of a trade-off of high- speed lead in of a horizontal line noise and a clamp. please check both characteristics and deter mine the optimal value. 7 clamp operation a clamp mistake is made to induce and data and pulse timing of a dummy clamp are set up. please see a margin with the time of alumnus clamp. take large gnd as much as possible. please separate an analog power supply and a digital power supply by l etc. please arrange an input pulse, a serial communication line, etc. not to jump in to an analog part. 8 the notes about hardware an adc output is extended for a long time, or 30 mhz or more in carrying out high-speed operation, it becomes easy to generate a ripple. in such a case, feed in about 100 ? into 12 adc output pins as dumping resistance in series, or please try reduction using differential code.
hd49343np/hnp preliminary r19ds0068ej0200 rev.2.00 page 22 of 22 jul 06, 2012 package dimensions 0.20 0.20 0.20 0.50 0.60 0.70 0.20 0.89 0.22 6.2 6.2 h e c h d c 1 0.17 0.25 0.05 0.5 0.17 0.22 0.27 0.95 0.05 e e a 1 maxnommin dimension in millimeters symbol reference d e a 2 a b b 1 x y z d z e l p y 1 t 6.0 6.0 0.040.02 0.005 1.0 1.0 1 c 2 1 p b 1 y y 1 x4 t 10 19 18 19 27 36 28 e d e d a a a c l b z z h e h d m p-vqfn36-6x6-0.50 0.07g mass[typ.] tnp-36/tnp-36v pvqn0036ka-a renesas code jeita package code previous code
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